1. Field of the Invention
This invention relates generally to integrated circuits, and more particularly to semiconductor devices used in electrostatic discharge applications.
2. Description of the Related Art
Most integrated circuit applications have some type of electrostatic discharge (ESD) circuitry that is used to absorb electrostatic charges that may inadvertently destroy circuit devices that operate at relatively low voltage levels. Typically, ESD circuitry is designed in an input/output (I/O) cell that includes circuitry for applying signals from an I/O pad into a core circuitry region. The I/O cell also typically includes amplification circuitry for amplifying and driving signals that are generated within the core circuitry out to the I/O pad that may be coupled to a lead of a packaged device.
FIG. 1A shows typical I/O circuitry that is used to interface with semiconductor circuits that are laid out in the core circuitry 110. As mentioned above, the I/O circuitry generally includes ESD circuitry that protects the first input gate 108 and the core circuitry 110 from high voltage charges that are commonly transferred by casual human handling. By way of example, if a person touches a lead or an electrical contact that is electrically connected to an I/O pad 102, a charge from the person's body can be transferred to tiny semiconductor devices lying within the core circuitry 110. As is well known, these human transferred charges are typically much greater than what the gate oxide of the first input gate 108 and the core circuitry 110 is capable of handling (and may cause some devices to be permanently destroyed). As a result, ESD circuitry is used to prevent such damage to the first input gate 108 and the core circuitry 110.
In this example, the I/O circuitry is capable of handling ESD events as well as normal input and output operations. During a normal input operation from the I/O pad 102, signals are transferred from the I/O pad 102 to an inverter 108, which assists in buffering the signals that are being passed to selected circuits that lie within the core circuitry 110. Normal output operations may be performed from within the core circuitry 110 out to the I/O pad 102, through one of a P-channel transistor 106 or an N-channel transistor 104. In some applications, the N-channel transistor 104 is only used for electrostatic discharge (ESD) operations, and therefore will not be used as an output device. When that is the case, the gate of the N-channel transistor 104 is coupled through a resistor 112 that is connected to ground (GND). A similar resistor "R" (not shown) can also be coupled to the gate of the P-channel transistor 106.
Accordingly, the transistor 104 is designed to receive a high voltage discharge during an ESD event through its drain terminal, which is caused to breakdown at the drain to bulk interface of the transistor 104. As will be illustrated below, the ability of the transistor 104 to enter into the breakdown state, and then shift into a snap-back operation enables the N-channel transistor 104 to adequately absorb the ESD event charge (i.e., without destroying circuits within the core circuitry 110). The snap-back characteristic is shown in FIG. 1C below, and illustrates that a lower voltage impedance is produced during snap-back, which therefore provides a lower resistance path for current to flow from the drain to the source that is connected to ground.
FIG. 1B shows a cross-sectional view of the prior art N-channel transistor 104 which has the pad 102 connected to a drain 124b. In this example, the N-channel transistor 104 is formed over a P-type substrate 120. The P-type substrate 120 typically has an acceptor atom concentration N.sub.A of about 10.sup.15 atoms per cm.sup.3. The semiconductor substrate 120 has a diffused P-well region 122 (i.e., P-). The diffused P-well region 122 typically has an acceptor atom concentration of about 10.sup.17 to about 10.sup.18 atoms per cm.sup.3 at the diffusion surface. As is well known, the acceptor atom concentration decreases as the acceptor atoms diffuse into the substrate. Diffused within the P-well region 122 are two N-type diffusion regions 124a and 124b. Diffusion region 124a functions as a source and diffusion region 124b functions as a drain of the N-channel transistor 104.
Also diffused into the diffusion region 122 is a P+ contact region 134 which provides electrical contact with the substrate through a conductive contact 132. The N-channel transistor 104 has a gate oxide and an overlying polysilicon gate 136, which lies between the N-type diffusion regions 124a and 124b. Deposited and/or grown over the substrate is an oxide layer 125, which has various contacts defining paths down to the N-channel transistor 104 and the substrate contact 134. In this manner, a contact 126 can make an electrical connection down to the drain diffusion region 124b, a contact 128 can make an electrical connection down to the gate 136, a contact 130 can make an electrical connection down to the source diffusion region 124a, and the contact 132 can make an electrical connection down to the substrate contact 134.
In typical cases, the polysilicon gate 136 is coupled to the resistor 112, which is then coupled to ground. The resistor 112 may be formed from the n+ or n-well diffusion or the polysilicon gate. Contact 130 is also coupled to ground so that the source can provide a path down to ground during an ESD event. The substrate contact 134 is also coupled to ground through the contact 132. As mentioned above, during an ESD event a charge is typically received through the I/O pad 102 and then coupled down to the drain 124b. If the ESD charge has positive polarity, charge will build up in the depletion region of the drain 124b. The electric field in the depletion region is greatest at a junction 123, which defines an interface between the drain and the bulk of the substrate within the P-well diffusion region 122, and when a critical value is reached, approximately 3.times.10.sup.5 volts/cm, avalanche breakdown of the junction occurs.
Initially, current that is produced from a positive charged ESD event will flow through a path of least resistance, which is a path 121 defined from the drain diffusion region 124b to the substrate contact 134, and then to ground. As the charge builds up in the depletion region of drain 124b on either side of the junction 123, the N-channel transistor 104 will begin to reach its breakdown at a point "A," as shown in FIG. 1C. In this example, it is assumed that the voltage between the gate 136 and the source 124a is equal to zero (i.e., V.sub.GS =0), and that breakdown will occur in the depletion region just under gate 136 when the voltage between the drain 124b and the source 124.sub.a reaches about 12 volts (i.e., V.sub.DS =12). Thus, at point A, the device will experience breakdown and then go into the aforementioned snap-back condition at a point "B" as drain current I.sub.D increases. The snapback occurs when source region 124 begins injecting electrons into substrate 122 due to current flowing through bulk resistance R1 and causing a forward bias voltage of 0.5V. These added electrons inject into the drain depletion region and cause the well known bipolar transistor snapback effect.
When snap-back occurs, current I.sub.D will then commence to flow from the drain 124b to the source 124a at a reduced resistance. Once this happens, the current I.sub.D will flow to ground through the contact 130, and the voltage between the drain 124b and the source 124a will decrease to about 8 volts. As the voltage continues to build up between the drain 124b and source 124a, the current I.sub.D flowing through the drain 124b will continue to increase up to a point "C." At point C, the N-channel transistor 104 may fall into what is known as a second breakdown. Unfortunately, a second breakdown can cause a destructive event by permanently damaging the N-channel transistor 104, thereby disabling the ESD protection provided for the first input stage 108 and the core circuitry 110 of FIG. 1A and causing the circuit not to meet its desired parameters.
In this example, point C occurs at a current I.sub.D1, but that point may be increased to a level shown as point D by appropriately placing the contact 126 to the drain 124b at a predetermined distance "D," as shown in FIG. 1D. That is, by separating the contact 126 by a distance D, a built-in ballast resistance is achieved. For example, a ballast resistor 142 is pictorially shown in FIG. 1E, and can therefore be used to delay the second breakdown until a point D.
FIG. 1E also shows how fixed positive charges 144 build up in the drain 124b and fixed negative charges 145 build up in substrate 122 causing formation of depletion region 140 around the junction 123 of the drain 124b and the P-well diffusion region 122. As pictorially shown, when the transistor 104 reaches a breakdown stage of point A as shown in FIG. 1C and causes current to flow through resistor R1, the source 124a will begin to inject electrons toward the junction 123 as source region 124a becomes forward biased. As is well known, this injection of electrons facilitates the flow of current from the drain 124b to the source 124a, and therefore causes the snap-back event that is illustrated as point B in FIG. 1C.
When a negative ESD charge is applied to drain region 124b with respect to substrate region 122, current is easily conducted to ground through a low impedance forward biased N+/P- junction. This condition is typically much easier to protect against than the previously described positive charge situation. In the design of high performance applications, there is always a need for robust ESD performing devices as well as a need for faster performing devices. Unfortunately, better performing ESD devices typically suffer in having higher input capacitance, which in turn reduces the switching speed of a device. As such, designers are often required to make a tradeoff between speed and good ESD performance.
For example, in order to place the contact 126 a distance D away from the gate 136 as shown in FIG. 1D, a larger drain 124b will be needed to ensure proper interconnection of the contact 126. As is well known, when the drain region 124b is increased, the junction capacitance Cj of the transistor increases. In general, the junction capacitance Cj includes two components, which are proportionally increased or decreased depending on the physical size of the diffusion drain region 124b. As pictorially shown, one component is the sidewall capacitance "C.sub.S " and another usually larger and more dominant component is the area capacitance "C.sub.A " (i.e., Cj=C.sub.S +C.sub.A).
Another capacitance component is the overlap capacitance "C.sub.OI " which is derived from the slight overlap of the gate 136 over the drain 124b. Another input capacitance component is that which is associated with a packaged device, in which the core circuitry 110, I/0 circuitry, and I/0 pad 102 are packaged within. This component of input capacitance is pictorially shown in FIG. 1B as "C.sub.PACK ". Of course, other parasitic components of input capacitance may also be present, in addition to the capacitance of the input gate 108 being protected.
Although there are various components which add up to produce a total input capacitance and thereby reduce the speed at which a particular integrated circuit can operate, the area capacitance "C.sub.A " of the drain region 124b will generally contribute the most to the total input capacitance. However, as mentioned above, a large physical drain region is needed in order to maintain the separation D between the contact 126 and the gate 136 (i.e., to provide improved ESD performance).
The area capacitance "C.sub.A " contributes the most to the total input capacitance component because the junction capacitance Cj is proportional to the square root of the acceptor atom concentration in the P-well diffusion region 122 (i.e., C.sub.j .alpha. .sqroot. N.sub.A) for a step junction, and the drain-substrate junction can be approximated as a step junction. As mentioned above, the P-well diffusion region 122 typically requires a concentration of about 10.sup.17 atoms per cm.sup.3 to about 10.sup.18 atoms per cm.sup.3 at the die surface. Unfortunately, to maintain a high level of ESD and switching performance, that range of acceptor atom concentration is required at the junction 123 and channel region under gate 136 to meet required ESD protection. The need to preserve sufficient contact-to-gate space for good ESD performance also contributes to higher values of C.sub.A than typical devices not having this constraint. As a result, the junction capacitance Cj must be maintained relatively high for good performing ESD devices, and therefore, the input capacitance will also remain relatively high. Thus, good ESD performing devices are traditionally slower because they have a higher input capacitance.
In view of the foregoing, what is needed is a transistor structure which provides a high level of ESD protection while also providing reduced input capacitance parameters.